Digital Electronics, Data Converters and Microprocessors — ESE E&T

Weightage: Digital electronics and microprocessors are a dependable, mostly numerical block in the E&T papers. The topics are rule-based, so success comes from a few fast habits: simplify with a K-map, count flip-flops from the modulus, and compute memory size from address lines.

1. Number systems

For $n$ bits in two's complement the range is $-2^{n-1}$ to $2^{n-1}-1$. A negative number is formed by inverting the bits and adding 1. Sign-magnitude and one's complement have two representations of zero, while two's complement has one.

Worked example. In 8 bits, $-5$ is $11111011$: invert $00000101$ to $11111010$ and add 1. The range is $-128$ to $+127$.

Gray code changes only one bit between adjacent values, which avoids glitches in position encoders. BCD stores each decimal digit in 4 bits.

2. Boolean algebra and K-maps

The key laws are De Morgan's: $\overline{A+B}=\bar{A}\bar{B}$ and $\overline{AB}=\bar{A}+\bar{B}$. Others are absorption ($A+AB=A$) and consensus ($AB+\bar{A}C+BC=AB+\bar{A}C$).

NAND and NOR are universal gates: any function can be built from either alone.

A Karnaugh map groups adjacent 1s in powers of two (1, 2, 4, 8) to find a minimal sum of products. Groups wrap around the edges, and don't care cells may be used to enlarge a group.

Worked example. $F(A,B,C)=\sum m(1,3,5,7)$ has 1s wherever $C=1$, so the single group of four gives $F=C$.

3. Combinational circuits

• Half adder: sum $=A\oplus B$ and carry $=AB$. Full adder: sum $=A\oplus B\oplus C_{in}$ and carry $=AB+C_{in}(A\oplus B)$.
• A ripple-carry adder is slow since the carry passes through every stage. A carry-lookahead adder computes carries in parallel.
• A multiplexer $2^n:1$ selects one of $2^n$ inputs, and it can implement any function of $n+1$ variables by using one variable as data input. A 4:1 mux therefore implements any three-variable function.
• A decoder activates one of $2^n$ outputs from $n$ inputs, and with an OR gate it implements functions. An encoder does the reverse. A comparator gives greater than, equal and less than.
• A hazard is a momentary glitch from unequal delays. A static hazard is removed by adding the consensus term.

4. Sequential circuits

Latches are level-sensitive and flip-flops are edge-triggered. Characteristic equations:

A JK flip-flop with $J=K=1$ toggles. If it is level-triggered and the pulse is long, it toggles repeatedly: the race-around condition, which edge triggering or a master-slave design cures.

Counters. An $n$-flip-flop binary counter has modulus $2^n$ (60 states need 6 flip-flops). An asynchronous (ripple) counter is simple but slower, since delays accumulate, while a synchronous counter clocks all stages together. A ring counter of $n$ flip-flops has modulus $n$ and a Johnson (twisted-ring) counter has modulus $2n$. A shift register moves data one place per clock and multiplies or divides by two.

Finite state machines. A Moore machine's output depends only on the state, and a Mealy machine's output depends on the state and input. Mealy usually needs fewer states.

Timing. The minimum clock period is $T\ge t_{pd}+t_{su}$, so with a propagation delay of 10 ns and set-up of 2 ns the maximum frequency is $1/12\text{ns}=83$ MHz. Set-up and hold times are windows around the clock edge in which the data must be stable.

5. Logic families

Noise margin is the tolerance of a gate to input noise. Fan-out is the number of gate inputs a gate can drive. CMOS power is mainly dynamic, $P=C{V}^{2}f$. Open-collector (open-drain) outputs allow a wired-AND and bus sharing, and tri-state outputs allow several drivers on one bus.

6. Data converters

A DAC with $n$ bits and reference $V_{ref}$ has a step of $V_{ref}/2^n$. A 4-bit DAC with 5 V reference has a step of $5/16=0.3125$ V. The R-2R ladder needs only two resistor values and so matches better than a binary-weighted network.

An ADC has quantisation error up to half a step. Types:

• Flash: one comparator per level ($2^n-1$), the fastest and the most hardware.
• Successive approximation: $n$ clock cycles for $n$ bits, a good balance.
• Dual-slope: slow but accurate and noise-rejecting, used in digital multimeters.

The sampling theorem needs a sampling rate of at least twice the highest signal frequency, and an anti-aliasing filter before the converter.

7. Memory

A memory with $n$ address lines has $2^n$ locations. A 1K $\times$ 8 memory has $2^{10}=1024$ locations of 8 bits, so it needs 10 address lines and 8 data lines.

Address decoding uses the upper address lines to generate chip selects. Programmable logic (PLA, PAL, CPLD, FPGA) lets a designer configure logic in the field.

8. The 8085 microprocessor

The 8085 is an 8-bit processor with a 16-bit address bus, so it addresses 64 KB. Address lines $A_0$ to $A_7$ are multiplexed with the data lines $A{D}_0$ to $A{D}_7$ and are separated by ALE and an external latch. Its internal clock is half the crystal frequency.

• Registers: the accumulator, flag register, B, C, D, E, H and L, with the pairs BC, DE and HL, plus the program counter and stack pointer.
• Flags: Sign, Zero, Auxiliary carry, Parity and Carry.
• Addressing modes: immediate, register, direct, register indirect and implied.
• Interrupts: TRAP (non-maskable, highest priority, edge and level), then RST 7.5, RST 6.5, RST 5.5 and INTR. TRAP and the three RST interrupts jump to fixed addresses (vectored), while INTR must supply an instruction such as RST or CALL from outside.
• Stack: it grows downward, and the instruction CALL pushes the return address.

Instruction timing counts T-states. A machine cycle (opcode fetch, memory read or write, I/O) has several T-states, and the opcode fetch normally has four. For the 8051 microcontroller, remember the 8-bit architecture, four I/O ports, two timers and on-chip memory.

Common traps

• Forgetting that two's complement is asymmetric. One more negative value than positive.
• Counting Johnson modulus as $n$. It is $2n$.
• Using $2^n$ comparators for a flash ADC. It is $2^n-1$.
• Mixing which 8085 interrupt is non-maskable. Only TRAP.
• Ignoring don't cares in the K-map.

Memory aids

• "Ring n, Johnson 2n": counter moduli.
• "Flash fastest, dual-slope accurate": ADC types.
• "2 to the n": memory locations from address lines.

Summary

Digital design starts with number representation and Boolean simplification by K-map. Combinational blocks such as adders, multiplexers and decoders are built from gates, and sequential designs from flip-flops with counters and finite state machines under set-up and hold constraints.

Converters trade speed and accuracy, memories are sized by address lines, and the 8085 is described by its registers, flags, interrupts and 64 KB address space.

Exam protocol

• Derive the modulus before counting flip-flops.
• Use a K-map for any function of four variables or fewer.
• Compute memory size from address and data lines.
• Check the clock period against propagation delay and set-up time.