"Machine Instructions & Addressing Modes" — Practice

Question 1

Which addressing mode requires the fewest memory accesses to obtain its operand?

Accepted Answer

C

Question 2

A machine has 32-bit instructions with a 6-bit opcode and two 5-bit register fields. How many bits remain for an immediate operand?

Accepted Answer

A

Question 3

Which is the defining characteristic of a load-store architecture?

Accepted Answer

B

Question 4

A machine has one-address instructions with a 16-bit word. Count the total memory accesses to execute ADD @X, where @ denotes full indirect addressing, assuming the accumulator holds one operand and receives the result.

Accepted Answer

Count every access, starting with the instruction itself.

Instruction fetch: 1 access, to read the ADD instruction containing the address field X.

Pointer fetch: full indirect means the address field X names a memory location that itself contains the operand's address. Reading that pointer costs 1 access.

Operand fetch: reading the actual operand from the address just obtained costs 1 access.

The addition then takes place between that operand and the accumulator, and the result is written back to the accumulator, which is a register and costs no memory access.

The total is 3 memory accesses.

For comparison, the same instruction with direct addressing would cost 2, since the address field is the operand's address and no pointer fetch is needed. With immediate addressing it would cost 1, the instruction fetch alone. The progression 1, 2, 3 across immediate, direct and indirect is worth carrying as a check.

Question 5

A processor runs a program in which 25 per cent of instructions are floating-point, taking 8 cycles each, while the other 75 per cent take 2 cycles. A redesign makes floating-point instructions take 4 cycles. Compute the old and new CPI and the speedup.

Accepted Answer

Average CPI is the weighted sum of the class CPIs.

Old CPI = 0.25 times 8 + 0.75 times 2 = 2.0 + 1.5 = 3.5.

New CPI = 0.25 times 4 + 0.75 times 2 = 1.0 + 1.5 = 2.5.

Instruction count and clock period are unchanged, so the speedup is the ratio of the CPIs: 3.5 divided by 2.5 = 1.4, a 40 per cent improvement.

Cross-check with Amdahl's law. Floating-point instructions consumed 2.0 of the original 3.5 cycles, so the fraction of time they occupied is f = 2.0/3.5 = 0.571, and they were sped up by a factor s = 2.

Amdahl gives S = 1 divided by (0.429 + 0.571/2) = 1 divided by 0.714 = 1.4, which matches exactly.

The limiting case is instructive: even making floating-point instructions free would give at most 1 divided by 0.429 = 2.33 times speedup, because the remaining 43 per cent of the time is untouched.

Question 6

On a byte-addressable machine with 4-byte instructions that increments the PC during fetch, a branch at address 5000 must transfer control to address 4800. What displacement must be encoded?

Accepted Answer

The displacement is measured from whatever the program counter holds when the addition is performed.

Because the machine increments during fetch, by the time the branch executes the program counter holds the address of the next instruction, which is 5000 + 4 = 5004.

The required target is 4800, so the displacement is 4800 minus 5004 = minus 204.

The encoded field must therefore hold minus 204 as a signed value, which needs at least 9 bits in two's complement, since 8 bits reach only to minus 128.

Had the machine used the current instruction's address instead, the displacement would have been 4800 minus 5000 = minus 200. The two answers differ by exactly one instruction length, and which is correct depends on the convention stated in the question.

The reason PC-relative is used here is position independence: if the entire code block were relocated, the distance of minus 204 would still reach the right target, whereas an absolute address of 4800 would not.

Question 7

A machine has 12-bit instructions and 3-bit address fields. It needs 4 three-address instructions, 255 two-address instructions and 16 one-address instructions. Does an encoding exist?

Accepted Answer

Work from the largest operand count downward, tracking the opcode space consumed and released at each level.

Three-address instructions use 9 bits for their three 3-bit address fields, leaving 3 bits of opcode. Three bits give 8 patterns, and 4 are needed, so 4 patterns remain unused.

Each unused pattern expands over the address field freed by dropping to two operands, which is 3 bits wide. So the space available at the two-address level is 4 times 2 to the 3 = 4 times 8 = 32 opcodes.

But 255 two-address instructions are required, and only 32 are available.

The encoding does not exist.

The requirement is impossible by a wide margin: satisfying it would need 255 divided by 8, which is 32 unused three-address patterns, but only 8 patterns exist in total at that level. Even allocating zero three-address instructions would leave 8 patterns expanding to 64 two-address opcodes, still far short of 255.

The general check worth extracting: at each level, available space equals unused patterns times 2 to the freed field width, and the requirement must fit before moving down.

Question 8

Evaluate the expression (A + B) * (C - D) / E on a zero-address stack machine and on a three-address machine. Compare the instruction counts.

Accepted Answer

For the stack machine, first convert the expression to postfix: A B + C D - * E /.

Now translate each postfix symbol. An operand becomes a PUSH and an operator becomes a stack operation consuming the top two entries.

PUSH A, PUSH B, ADD, PUSH C, PUSH D, SUB, MUL, PUSH E, DIV, and finally POP to store the result.

That is 10 instructions: 5 pushes, 4 arithmetic operations and 1 pop.

For the three-address machine, each arithmetic instruction names both sources and the destination, so no intermediate movement is needed.

ADD T1, A, B. SUB T2, C, D. MUL T3, T1, T2. DIV RESULT, T3, E.

That is 4 instructions.

The stack machine needs 2.5 times as many instructions but each is far shorter, since a stack operation carries no address field at all while a three-address instruction carries three. This is exactly the trade between the instruction count and clock period terms of the execution-time identity, and it is why stack machines were attractive when instruction memory was the scarce resource.

Question 9

Explain why a machine that stores the return address in a dedicated link register can still support recursion, and what the compiler must do.

Accepted Answer

A link register alone cannot support recursion, because a second call overwrites the first return address. But it can support recursion if the compiler saves the register onto a stack, which is exactly what real link-register architectures require.

The sequence is precise. On entry, a subroutine that will itself make a call pushes the current link register value onto the stack as part of building its activation record. It then performs its own calls freely, each of which overwrites the link register. Before returning, it pops the saved value back into the link register and branches to it.

A leaf subroutine, one that makes no calls of its own, needs none of this. Its link register is never overwritten, so it can return directly without touching memory at all.

That asymmetry is the point of the design. The common case of a leaf call becomes a register-only operation with no memory traffic, and only non-leaf calls pay for a save and restore. A machine that always pushed the return address to memory would pay that cost on every call including leaves.

The same reasoning extends to the rest of the activation record: parameters, locals and callee-saved registers are stacked only when the subroutine actually needs per-invocation copies, which is what makes the convention worth its complexity.

Practice — "Machine Instructions & Addressing Modes"

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