"I/O Interface: Interrupt & DMA Mode" — Practice

Question 1

In which I/O method does the processor never touch the individual data bytes?

Accepted Answer

C

Question 2

Which interrupt type cannot be disabled by software?

Accepted Answer

A

Question 3

Which DMA mode transfers data only during bus cycles the processor is not using?

Accepted Answer

C

Question 4

A hard disk transfers at 16 MB per second in 8 KB blocks. Interrupt-driven transfer costs 50 cycles per 4-byte word; DMA costs 1200 cycles per block. On a 3 GHz processor, compare the overhead as a percentage of processor time.

Accepted Answer

Start with interrupt-driven transfer. At 16 MB per second and 4 bytes per word, the word rate is 16 times 10 to the 6, divided by 4, which is 4 million words per second.

At 50 cycles each, that is 200 million cycles per second.

As a fraction of 3 GHz, the overhead is 200 million divided by 3 billion, which is 6.67 per cent of the processor.

Now DMA. At 16 MB per second in 8 KB blocks, the block rate is 16 times 10 to the 6, divided by 8192, which is about 1953 blocks per second.

At 1200 cycles each, that is about 2.34 million cycles per second.

As a fraction of 3 GHz, the overhead is 0.078 per cent.

DMA reduces the processor overhead by a factor of about 85. The reason is entirely structural: interrupt-driven transfer pays per word while DMA pays per block, and an 8 KB block contains 2048 words.

What this calculation excludes is the bus cost. DMA still consumes one bus cycle per word transferred, which is a bandwidth cost rather than a processor-time cost, and it must be computed separately.

Question 5

A DMA controller in cycle-stealing mode transfers at 8 MB per second over a 16-bit bus with a 12 ns bus cycle. What percentage of bus bandwidth does it consume?

Accepted Answer

A 16-bit bus moves 2 bytes per cycle.

At 8 MB per second, the required word rate is 8 times 10 to the 6, divided by 2, which is 4 million bus cycles per second.

Each stolen cycle occupies 12 ns, so the total bus time consumed per second is 4 million times 12 ns = 48 million ns, which is 48 ms.

As a fraction of one second, that is 4.8 per cent of the bus.

The processor therefore retains about 95 per cent of the bus bandwidth, and its actual slowdown is smaller still, since it stalls only in the stolen cycles where it happened to want the bus itself.

Two comparisons make the figure meaningful. Doubling the bus to 32 bits would halve the cycle count and therefore halve the bus consumption to 2.4 per cent. And in burst mode the same total bus time would be taken in contiguous blocks rather than spread out, giving the same average but far worse worst-case latency for the processor.

Question 6

Six devices share an interrupt system. Compare the number of signal lines and the flexibility of daisy chaining against independent requesting.

Accepted Answer

Daisy chaining uses a single interrupt request line shared by all devices, plus a single acknowledge line that passes serially through them.

That is 2 lines in total, independent of the device count.

The acknowledge signal enters the first device; if that device has a pending request it intercepts the signal and is serviced, otherwise it passes the signal on. Priority is therefore fixed by physical position on the chain, and changing it requires rewiring the hardware.

Independent requesting gives each device its own request line and its own acknowledge line, so 6 plus 6 = 12 lines, with a priority encoder resolving simultaneous requests.

Priority is programmable by configuring the encoder, identification is immediate because the requesting device is known from which line asserted, and no serial propagation delay is incurred.

The trade is 2 lines against 12, and fixed against programmable priority. For a small fixed set of devices with a natural priority order, daisy chaining is entirely adequate. For a system where devices are added, removed or reprioritised, independent requesting is the only practical choice, which is why modern interrupt controllers use it.

Question 7

A processor at 2 GHz must service a device that becomes ready every 2 ms. Polling costs 15 cycles per check; interrupt service costs 400 cycles. Compare the overhead, and state at what device rate polling becomes preferable.

Accepted Answer

Under polling, the processor must check often enough not to miss a ready signal. If it checks continuously, it performs 2 ms divided by (15 cycles at 0.5 ns each, which is 7.5 ns) checks, which is about 267,000 checks per event, consuming essentially all the processor time.

Even checking only often enough to guarantee detection within a reasonable window, the overhead scales with how tight that window must be.

Under interrupts, each event costs 400 cycles and events occur 500 times per second, giving 200,000 cycles per second. As a fraction of 2 billion cycles per second, that is 0.01 per cent.

Interrupts win overwhelmingly here, by roughly four orders of magnitude.

Now find the crossover. Polling becomes preferable when the device is ready so often that a check almost always succeeds immediately, so the polling cost per byte approaches its 15 cycles while the interrupt cost stays at 400.

That happens when the expected number of checks per successful transfer falls below 400 divided by 15, which is about 27. Equivalently, when the device is ready within roughly 27 poll intervals, or about 200 ns.

So for a device with sub-microsecond latency — a fast network interface being drained under load, for example — polling genuinely beats interrupts, which is why high-performance network drivers switch to polling when traffic is heavy.

Question 8

Explain the two distinct cache hazards created by memory-mapped I/O and by DMA, and how each is resolved.

Accepted Answer

The first hazard concerns device registers under memory-mapped I/O. A cache is built on the assumption that a memory location changes only when the processor writes to it, and a device register violates that assumption because the device alters it independently — a status bit setting when data arrives, for instance.

If the register were cacheable, the first read would load the value into the cache and every subsequent read would hit and return the stale copy. A polling loop would spin forever on a value that had stopped reflecting reality.

The write direction is equally broken under a write-back cache. A command written to a device register would sit dirty in the cache and reach the device only on eviction, at an unpredictable time, or never if the line is discarded.

The resolution is to mark the device address region non-cacheable, so every access reaches the device directly. Isolated I/O avoids the hazard by construction, since its separate address space is outside the cache's coverage.

The second hazard concerns ordinary memory buffers under DMA, and it exists regardless of the I/O addressing scheme. A DMA controller writing incoming data into a memory buffer bypasses the cache entirely, so any cached copy of that buffer becomes stale and a subsequent processor read returns old data. In the outgoing direction, data the processor wrote may still sit dirty in the cache while DMA reads the stale memory copy.

The resolutions are to invalidate the affected cache lines before reading a DMA-filled buffer and flush them before starting a DMA read, or to route DMA through a coherent path that snoops the cache automatically.

Question 9

A system contains a memory responding in 8 ns and a peripheral responding in 240 ns. Compare a synchronous bus, a synchronous bus with wait states, and an asynchronous bus.

Accepted Answer

On a plain synchronous bus, every transfer occupies a fixed number of clock periods, and the period must be long enough for the slowest responder. With a 240 ns peripheral, the period must be at least 240 ns.

Every memory access then also takes 240 ns despite the memory needing only 8, so the fast memory is slowed by a factor of 30. The bus is correct and badly inefficient.

With wait states, the bus runs at a period suited to the fast device — say 10 ns — and a slow device asserts a wait signal that extends its own transfer by whole periods. The peripheral needs 240 ns, so it inserts enough wait states to cover 24 periods.

Memory accesses now complete in one 10 ns period, recovering essentially all the fast memory's speed, while the peripheral takes about as long as it did before. The cost is the wait mechanism and the requirement that slow devices assert it correctly.

On an asynchronous bus, each transfer uses a request-acknowledge handshake and completes when the responder signals it has finished. The memory access takes roughly 8 ns plus the handshake round-trip, and the peripheral takes 240 ns plus the same. Neither is slowed by the other, and no clock period must be chosen in advance.

The cost is that handshake overhead on every transfer, which for the 8 ns memory may be comparable to the access itself, plus more complex control logic and greater sensitivity to signal skew. This is why real systems overwhelmingly use synchronous buses with wait states rather than fully asynchronous ones.

Practice — "I/O Interface: Interrupt & DMA Mode"

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