"ALU, Data-path & Control Unit" — Practice

Question 1

A computer has 1 M addressable locations and a 32-bit data bus. What are the widths of the memory address register and the memory buffer register?

Accepted Answer

A

Question 2

Which control unit design generates control signals using combinational logic driven by the opcode and a timing counter?

Accepted Answer

B

Question 3

After an 8-bit two's complement addition of 100 and 50, which flags are set?

Accepted Answer

B

Question 4

On a single-bus datapath, write the micro-operations for STORE R1, X where X is a direct address, and count the total cycles including fetch.

Accepted Answer

Fetch takes 3 cycles as usual: MAR gets PC; MBR gets memory contents while PC increments; IR gets MBR.

Now the execute phase, remembering that only one value can travel on the bus per cycle.

Cycle 4: MAR gets the address field of the instruction register, sending X to the memory address register.

Cycle 5: MBR gets R1, moving the value to be written into the memory buffer register.

Cycle 6: memory at MAR gets MBR, performing the write.

The execute phase takes 3 cycles and the whole instruction takes 6.

Note that cycles 4 and 5 cannot be merged on a single-bus machine, because both are transfers over the one bus. On a two-bus datapath they could proceed simultaneously, cutting the execute phase to 2 cycles, which is the resource-conflict rule applied directly.

Question 5

A microprogrammed control unit has 26 control signals and a control memory of 2048 words. Compute the horizontal microinstruction width if each word carries an explicit next-address field.

Accepted Answer

Two fields must be sized.

The control field in a horizontal format has one bit per control signal, so it is 26 bits.

The next-address field must name any location in the control memory. With 2048 words, that requires the base-two logarithm of 2048, which is 11 bits.

The microinstruction width is 26 plus 11 = 37 bits.

The control memory therefore holds 2048 words of 37 bits, which is 75,776 bits, roughly 9.25 KB.

Two checks are worth doing. The next-address field must cover the whole control memory, not just the current microroutine, since a mapping or branch can jump anywhere. And if the design used an incremented counter instead of an explicit next-address field, the width would drop to 26 bits plus whatever branch mechanism is provided, at the cost of requiring microroutines to occupy contiguous locations.

Question 6

Compare the number of execute cycles for R1 gets R2 plus R3 on single-bus, two-bus and three-bus datapaths, and explain the difference.

Accepted Answer

The operation needs three transfers: two operands into the ALU and one result out.

On a single-bus datapath, all three transfers contend for the one bus. Cycle 1 moves R2 into the ALU's holding register Y. Cycle 2 places R3 on the bus as the second ALU input and latches the sum in the output register Z. Cycle 3 returns Z to R1. That is 3 cycles.

On a two-bus datapath, both operands can travel simultaneously on the two buses, so the ALU receives them and computes in cycle 1. The result must then be written back over one of the buses in cycle 2. That is 2 cycles.

On a three-bus datapath, two source buses carry the operands while a separate destination bus carries the result, all in the same cycle, provided the ALU is combinational and settles within the clock period. That is 1 cycle.

The pattern is exactly the resource-conflict rule: each additional bus removes one contention and therefore one cycle. The cost is wiring and multiplexer complexity, which grows roughly with the product of the number of buses and the number of registers, which is why three buses is the practical limit for a simple design.

Question 7

A machine has 50 control signals partitioned into mutually exclusive groups of sizes 6, 12, 8, 15 and 9. Compute the vertical control field width and compare with horizontal, then state the condition under which the vertical encoding is valid.

Accepted Answer

In a vertical format each group becomes one field, and the field must encode every signal in the group plus a null code meaning no signal in this group is asserted.

Group of 6 needs 7 codes, requiring 3 bits.
Group of 12 needs 13 codes, requiring 4 bits.
Group of 8 needs 9 codes, requiring 4 bits.
Group of 15 needs 16 codes, requiring 4 bits.
Group of 9 needs 10 codes, requiring 4 bits.

The vertical control field is 3 + 4 + 4 + 4 + 4 = 19 bits.

The horizontal control field would be 50 bits, one per signal.

The saving is 31 bits per microinstruction, about 62 per cent of the control field, multiplied by every word in the control memory.

The validity condition is strict: the signals within each group must genuinely never require simultaneous assertion. If any two signals in the group of 15, say, ever needed to be active in the same cycle, the vertical format could not express it, and the microprogram would need an extra microinstruction to assert them in successive cycles. That extra length can erase the memory saving, which is exactly the width-against-length trade. The encoding also costs a decoder on the critical path, adding gate delay to every cycle.

Question 8

Explain why the fetch phase can be identical for every instruction, and what changes when the machine supports variable-length instructions.

Accepted Answer

Fetch is identical because it does not depend on what the instruction is. It reads the word at the address in the program counter, advances the program counter, and deposits the word in the instruction register. Nothing in that sequence requires knowing the opcode, which is precisely why decoding comes afterwards.

That uniformity is what makes fetch worth optimising once. It can be hardwired even in an otherwise microprogrammed machine, and in a pipelined design it becomes a fixed first stage that runs for every instruction without variation.

Variable-length instructions break the uniformity in two ways. First, the amount to fetch is not known until part of the instruction has been decoded, so fetch and decode become interleaved rather than sequential. A machine may fetch one word, examine the opcode to learn the total length, then fetch the remainder.

Second, the program counter increment is no longer a fixed amount. It must be the actual instruction length, which is known only after partial decoding, so the increment cannot share the first read cycle as it does on a fixed-length machine.

Both effects lengthen the front of the pipeline and make it irregular, which is the concrete reason RISC designs adopted fixed-length encoding. Modern variable-length implementations pay the cost once by predecoding instructions into a fixed internal form and caching the result.

Question 9

A design team must choose between hardwired and microprogrammed control for a processor with 40 instructions, each needing between 3 and 12 cycles. State the trade-offs and what would decide the choice.

Accepted Answer

Hardwired control makes each signal a Boolean function of the opcode, timing state and flags. Its advantage is speed, since no memory sits in the control path and signals appear after one level of gate delay, which directly shortens the clock period. Its area is small for a small instruction set. Its disadvantage is that any change to an instruction requires redesigning and refabricating combinational logic, and the logic complexity grows quickly with instruction count and with the variability of cycle counts.

Microprogrammed control stores the signals in a control memory and reads one word per cycle. Its advantage is flexibility: adding or correcting an instruction is writing a microroutine, and the same datapath can implement a different instruction set entirely. Its disadvantage is the control memory read on the critical path of every cycle, which lengthens the clock period.

For this design, the spread from 3 to 12 cycles is the deciding factor. Highly variable cycle counts mean the hardwired timing logic must distinguish many states per instruction, and the combinational complexity grows roughly with the total number of distinct state-opcode combinations. Forty instructions averaging perhaps seven cycles gives on the order of 280 such combinations, which is well into the territory where microprogramming is easier to get right and to modify.

The historical resolution matches: complex, variable-cycle instruction sets were microprogrammed, and when designers wanted a short clock period they simplified the instruction set until hardwired control became practical, which is the RISC decision.

Practice — "ALU, Data-path & Control Unit"

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